1. Field of the Invention
The present invention relates generally to a method of forming a capacitor for a semiconductor device, and more particularly to a method of forming a capacitor for a semiconductor device using a silicon germanium layer as a mold layer.
A claim of priority is made to Korean Patent Application No. 2004–17504 filed on Mar. 16, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
As semiconductor devices such as dynamic random access memory (DRAM) have become increasingly integrated, a significant amount of research has gone into developing chips with a certain amount of capacitance within an increasingly minute area. In particular, researchers have worked to create smaller and smaller memory cells having a predetermined capacitance.
From a theoretical view, three main classes of methods are known to increase the capacitance of a capacitor: (1) using a material with a high dielectric constant for a dielectric layer in the capacitor, (2) enlarging the effective area of the capacitor, and (3) reducing the distance between upper and lower electrodes of the capacitor.
The effective area of a capacitor can be increased by deforming the surfaces of the capacitor or by increasing the height of the capacitor's storage electrodes. However, due to the high cost associated with manufacturing capacitors with deformed or irregular surfaces, more research has focused on increasing the height of storage electrodes.
Recently, capacitors have been developed with storage electrode heights greater than about 2000 Å in order to obtain sufficient capacitance for small DRAM cells.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method of forming a capacitor for a semiconductor device.
Referring to FIG. 1A, a device isolation trench 12 is formed in a semiconductor substrate 10, thereby defining an active region in semiconductor substrate 10. An active device is formed on the active region, and a MOS transistor is used as an exemplary active device for purposes of illustration.
The MOS transistor comprises a gate electrode in which a polysilicon layer 16 and a tungsten silicide layer 18 are sequentially stacked on a gate oxide layer 14. A first sidewall spacer 20 and a first mask layer 22 protect the gate electrode during subsequent processing. Dopants are implanted in surface portions of the active region using the gate electrode as an implantation mask, thereby forming source/drain regions (not shown) in the active region.
A contact hole is then formed on the source/drain regions using a self-aligned contact (SAC) process. The contact hole is filled with a conductive material such as polysilicon to thereby form contact plugs 24 and 26. A chemical mechanical polishing (CMP) process is used to separate contact plugs 24 and 26 from each other, and thus each of contact plugs 24 and 26 is positioned and functions independently from the other.
A first insulation layer 28 is then formed on semiconductor substrate 10 to a thickness sufficient to cover contact plugs 24 and 26. First insulation layer 28 is planarized using a conventional CMP process.
A bit line contact hole is formed in first insulation layer 28 to expose contact plug 24 (a drain contact plug). The bit line contact hole is filled with a conductive material to thereby form a bit line 30. A second sidewall spacer 32 and a second mask layer 34 are formed to protect bit line 30.
A second insulation layer 36 is formed on semiconductor substrate 10 to a thickness sufficient to cover bit line 30, and a conventional CMP process is used to planarize a surface of second insulation layer 36.
An opening is formed in second insulation layer 36 using a photolithography process, and polysilicon is used to fill the opening, thereby forming a contact plug 37. A nitride layer is formed on second insulation layer 36 and contact plug 37 to form an etch stop layer 38. An oxide layer 40 functioning as a mold layer during the formation of a storage electrode is then formed on etch stop layer 38 to a thickness of at least about 20000 Å. Polysilicon is then deposited on oxide layer 40 to form a hard mask layer, and a photoresist layer is formed on the hard mask layer. The photoresist layer is patterned using a conventional photolithography process, and thus a photoresist pattern (not shown) is formed in such a manner that a desired capacitor area is defined. The hard mask layer is dry-etched using the photoresist pattern as an etching mask to form a hard mask pattern 42. The photoresist pattern is completely removed using an ashing and stripping process(es).
Referring to FIG. 1B, oxide layer 40 and etch stop layer 38 are anisotropically etched by an etching process using hard mask pattern 42 an etching mask to form an opening 44 through which a top surface of contact plug 37 is exposed.
An upper portion 44a of opening 44 is larger than a lower portion 44b of opening 44, and hence a critical dimension (CD) associated with the bottom portion of opening 44 is smaller than a CD associated with the top portion of opening 44. This result occurs because the etch rate is reduced as the etching process advances due to a loading effect, thereby causing the etch rate applied to the lower portion 44b to be less than that applied to the upper portion 44a. In other words, the resulting sidewalls of opening 44 lean somewhat outward, and thus as opening 44 descends, the difference between the CD of the bottom and top portions of opening 44 becomes greater. That is, the difference between the CD of the bottom and top portions of opening 44 increases as the height of the to-be-formed storage electrode increases.
After opening 44 is formed, a polysilicon layer 46 is formed to a uniform thickness on hard mask pattern 42 and sidewalls of opening 44 as shown in FIG 1C.
Referring to FIG. 1D, a sacrificial insulation layer (not shown) is formed on polysilicon layer 46 to a thickness sufficient to fill opening 44. Portions of sacrificial insulation layer 48 and polysilicon layer 46 are then selectively removed and planarized until a top surface of an etched oxide layer 40a is exposed, leaving only a portion of sacrificial insulation layer in opening 44 to form a sacrificial insulation pattern 48. Accordingly, capacitor nodes associated with different transistor cells are separated from each other.
Referring to FIG. 1E, etched oxide layer 40a and sacrificial insulation pattern 48 are removed by a wet etching process. At this point, a storage electrode 46a is complete. Of note, a top portion of storage electrode 46a having width “A” is larger than a width “B” associated with a bottom portion of storage electrode 46a. 
A dielectric layer (not shown) and a plate electrode (not shown) are then formed to cover storage electrode 46a, thereby completing a capacitor for a semiconductor device such as a DRAM.
Unfortunately, the foregoing, conventional method of forming a capacitor has a number of problems—some of which will be described in the following paragraphs.
First, after opening 44 is formed using hard mask pattern 42 as an etching mask, an inspection process is often performed using a scan electron microscope (SEM) to detect whether or not opening 44 is sufficiently opened. However, if hard mask pattern 42 were left in place, this inspection process would be obstructed, and thus hard mask pattern 42 must be removed prior to inspection of the opening 44. This requirement adds an additional process step to the method used to form the capacitor.
Second, the CMP process used to obtain node separation is expensive, and yet it cannot be replaced with a less expensive dry etching process, such as an etch-back process, for a number of reasons. In general, hard mask pattern 42 has various sizes, and where the dry etching process is performed, an etch rate is greater for a larger pattern than for a smaller pattern. Accordingly, where hard mask pattern 42 is relatively large, it is commonly over-etched, thereby partially removing an upper portion “C” of polysilicon layer 46, (see FIG. 1D), and hence reducing the size of storage electrode 46a. Therefore, the CMP process cannot be replaced in the conventional method with an etch-back process to obtain node separation. As a result, the manufacturing process for the capacitor can be prohibitively expensive.
Third, where a wet etching process is performed to remove sacrificial insulation layer 48 and etched oxide layer 40a following node separation, an etchant used in the wet etching process may infiltrate a boundary surface “D” (see FIG. 1E) between storage electrode 46a and etch stop pattern 38a. Because of this, second insulation layer 36 is also etched away by the infiltrated etchant and storage electrode 46a typically brakes.
Fourth, storage electrode 46a has a top portion with a width “A” and a bottom portion with a narrower width “B” (see FIG. 1E) due to a loading effect occurring in the etching process used to form opening 44. In other words, storage electrode 46a has a shape similar to an inverted triangle, which makes it structurally unsound. Accordingly, where the cell area is reduced and the storage electrode of the capacitor becomes very high, storage electrode 46a is easily broken by its own weight and awkward structure. In addition, when a wafer including storage electrode 46a is transferred for subsequent processing, even the slightest external impact may brake the electrode. Where storage electrode 46a is broken, it often makes contact with an adjacent storage electrode thereby generating a 2-bit (or 2-cell) failure in the context of a DRAM device.
Various studies have been conducted in attempts to effectively address the above problems. For example, U.S. Pat. No. 6,583,056 ('056) discloses a storage electrode including a double layer as a mold layer. The mold layer disclosed in '056 includes a lower mold layer into which impurities are implanted and an upper mold layer into which impurities are not implanted. The storage electrode disclosed in '056 is formed to have a stable shape by using upper and lower layers having different etch rates.
However, the storage electrode of '056 has a number of problems. For example, impurities are non-uniformly distributed on the mold layer in spite of the provision for heat treatment, and therefore the opening typically has ajar shape due to the non-uniform distribution of the impurities. In addition, the impurities tend to migrate into a contact plug during the heat treatment, thereby altering electrical resistance of the contact plug. In addition, the implanted impurities deteriorate characteristics of the active device (e.g. a transistor), causing such problems as the short channel effect.
Korean Publication Patent No. 2001–11167 ('167) discloses a single cylinder stacked capacitor including a double layer as a mold layer. The mold layer in '167 includes a lower mold layer comprising boron phosphorus silicate glass (BPSG) and an upper mold layer comprising plasma-enhanced tetraethylorthosilicate (PETEOS). The single cylinder stacked capacitor in '167 is formed to have a stable shape using upper and lower layers having different etch rates.
However, the storage electrode of '167 also has various problems as follows. The etch selectivity of the BPSG layer is about 2:1 relative to the PETEOS layer, and therefore an increase in the CD of a bottom of an opening requires an increase in the CD of a top of the opening. Accordingly, adjacent storage electrodes tend to be very close to each other and as a result they often generate 2-bit failures with even slight external impact.
In addition, where the concentration of the boron or phosphorus is increased in order to improve an etch rate of the BPSG layer, an etching polymer is likely to be formed during a dry-etching process, and thus the opening is generally not large enough, which is a well known phenomenon called a “not-open” failure.
In order to overcome at least the failings of the conventional methods described above, what is needed is a new method of forming a capacitor for a semiconductor device.